We had planned on adding division and add w/ carry, but there has been a change. Since the divider opcode took quite a while, we will be covering how to get the divider working from the ground up. This will be done using the ISE simulator and simple test bench code. We will cover the divider (version 3 and version 4) and also simulate the CPU itself.

We should not need the actual boards for this part. Even so, I suggest bringing them in case we have time at the end of class.

Required Items:
1. Laptop with Xilinx ISE installed. Please ensure you already have the ISE installed!! We will not have time to wait for the install process to complete (it usually takes 15-30 minutes). Check out http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html and download the ISE Design Suite for your OS.
2. Some Xilinx Spartan 6 or greater FPGA development board (must be Xilinx!!). We prefer the Mojo or Digilent Nexys3.
3. USB cable for your FPGA dev board.

We are to a point in the class where anyone wishing to join will need to E-Mail fpga@unallocatedspace.org. The reason being that we will need to verify that you know VHDL well, and have a development board already.

Because of the cost of FPGA dev boards, we will not have extras. If you have questions about what board to get, please E-Mail fpga@unallocatedspace.org.

We have recently been given ‘academic’ status from Digilent Inc (http://www.digilentinc.com). This means that the instructor can purchase boards from Digilent at the academic price. This discount will only apply to people who are attending the class regularly!

Since the space runs off of donations, we would like to mention that the recommended donation for this class is $5. It is by no means a requirement! Attendance to the space, and this class, is 100% free to all!