We will continue working with Serial/EPP data transfers. Here are the goals based on dev board type:

Mojo:
1. Create a FIFO to buffer data being written to the serial (from FPGA to computer)
2. Write data as quickly as possible to the FIFO until it is full, then wait for the FIFO to become empty and then add more data (most likely a counter)
3. Implement a FIFO for input data buffering.

Basys:
1. Create a RAM block to store X registers of data.
2. Read and write data to and from these registers.
3. Create ‘op codes’ that can be stored in the first register that will then cause operations on other registers. Also set a register to be a flag for an operation being complete. Example: Put 0x01 in register 2. 0x02 in register 3, then 0xff in register 1 (0xff being the flag for addition). When register 4 is non-zero, then the addition is complete.

This class is closed to new members. If you already know VHDL and have a Basys or Mojo based board, please contact fpga@unallocatedspace.org to get into the class. We are currently to far along in the class for new folks to join without prior knowledge of VHDL 🙁

Since the space runs off of donations, we would like to mention that the recommended donation for this class is $5. It is by no means a requirement! Attendance to the space, and this class, is 100% free to all!